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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com 10-pin, 24-bit, 192 khz stereo d/a converter features ! multi-bit delta-sigma modulator ! 24-bit conversion ! automatically detects sample rates up to 192 khz. ! 105 db dynamic range ! -90 db thd+n ! low clock-jitter sensitivity ! single +3.3 v or +5 v power supply ! filtered line-level outputs ! on-chip digital de-emphasis ! popguard ? technology ! small 10-pin tssop package description the cs4344 family members are complete, stereo dig- ital-to-analog output systems including interpolation, multi-bit d/a conversion and output analog filtering in a 10-pin package. the cs4344/5/6/8 support all major audio data interface formats, and the individual devices differ only in the supp orted interface format. the cs4344 family is based on a fourth order multi-bit delta-sigma modulator with a linear analog low-pass fil- ter. this family also includes auto-speed mode detection using both sample rate and master clock ratio as a method of auto-selecting sampling rates between 2 khz and 200 khz. the cs4344 family contains on-chip digital de-empha- sis, operates from a single +3.3 v or +5 v power supply, and requires minimal support circuitry. these features are ideal for dvd players & recorders, digital televi- sions, home theater and set top box products, and automotive audio systems. the cs4344 family is available in a 10-pin tssop package in both commercial (-10 to +85 c) and auto- motive grades (-40 to +85 c). please see section 8. ?ordering information? on page 23 for complete details. pcm serial interface multibit ? modulator interpolation filter internal voltage reference switched capacitor dac and filter serial audio input right output left output switched capacitor dac and filter de-emphasis multibit ? modulator interpolation filter 3.3 v or 5 v september '05 ds613f1 cs4344/5/6/8
2 ds613f1 cs4344/5/6/8 table of contents 1. pin descriptions ........................................................................................................... ................... 4 2. characteristics and specificat ions .......... ................. ................ ................ ................ ........... 5 specified operating conditions ................................................................................................ ... 5 absolute maximum ratings ...................................................................................................... ........ 5 dac analog characteristics .................................................................................................... ...... 6 dac analog characteristics - all modes .................................................................................. 6 combined interpolation & on-chip analog filter response ............................................. 7 digital input characteristics ................................................................................................. ...... 8 power and thermal characteristics ........................................................................................ 8 switching characteristics - serial audio interface ........................................................... 9 3. typical connection diagram ................................................................................................. .. 11 4. applications ............................................................................................................... .................... 12 4.1 master clock .............................................................................................................. ................... 12 4.2 serial clock .............................................................................................................. .................... 12 4.2.1 external serial clock mode .............................................................................................. ... 12 4.2.2 internal serial clock mode .............................................................................................. .... 12 4.3 de-emphasis ............................................................................................................... ................. 15 4.4 initialization and power-down ............................................................................................. ......... 15 4.5 output transient control .................................................................................................. ............ 15 4.5.1 power-up ................................................................................................................ ............ 15 4.5.2 power-down .............................................................................................................. .......... 15 4.6 grounding and power supply decoupling .................................................................................... 1 7 4.7 analog output and filtering ............................................................................................... ........... 17 5. filter plots ............................................................................................................... ...................... 18 6. parameter definitions ...................................................................................................... .......... 21 7. package dimensions ......................................................................................................... ........... 22 8. ordering information ....................................................................................................... ......... 23 8.1 functional compatibility .................................................................................................. ............. 23 8.2 selection guide ........................................................................................................... ................. 23 9. revision history ........................................................................................................... ................. 24
ds613f1 3 cs4344/5/6/8 list of figures figure 1. output test load .................................................................................................... ..................... 8 figure 2. maximum loading ..................................................................................................... ................... 8 figure 3. external serial mode input timing ................................................................................... .......... 10 figure 4. internal serial mode input timing ................................................................................... ........... 11 figure 5. internal serial clock generation .................................................................................... ............ 11 figure 6. recommended connection diagram ...................................................................................... ... 12 figure 7. cs4344 data format (i 2 s) ......................................................................................................... 14 figure 8. cs4345 data format (left justified) ................................................................................. ........ 14 figure 9. CS4346 data format (right justified 24) ............................................................................. ..... 15 figure 10. cs4348 data form at (right justified 16) ............................................................................ .... 15 figure 11. de-emphasis curve (fs = 44.1khz) ........ ........................................................................... ..... 16 figure 12. cs4344/ 5/6/8 initialization and power-down sequence .......................................................... 17 figure 13. single s peed stopband rejection .................................................................................... ....... 19 figure 14. single speed transition band ....................................................................................... .......... 19 figure 15. single speed transition band ....................................................................................... .......... 19 figure 16. single speed passband ripple ....................................................................................... ........ 19 figure 17. double speed stopband rejection .................................................................................... ...... 20 figure 18. double speed transition band ....................................................................................... ......... 20 figure 19. double speed transition band ....................................................................................... ......... 20 figure 20. double speed passband ripple ....................................................................................... ....... 20 figure 21. quad speed stopband rejection ...................................................................................... ...... 21 figure 22. quad speed transition band ......................................................................................... .......... 21 figure 23. quad speed transition band ......................................................................................... .......... 21 figure 24. quad sp eed passband ripple ......................................................................................... ........ 21
4 ds613f1 cs4344/5/6/8 1. pin descriptions pin name # pin description sdin 1 serial audio data input ( input ) - input for two?s complement serial audio data. dem /sclk 2 de-emphasis/external serial clock input ( input ) - used for de-emphasis filter control or external serial clock input. lrck 3 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. mclk 4 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. vq 5 quiescent voltage ( output ) - filter connection for internal quiescent voltage. filt+ 6 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. aoutl 7 left channel analog output ( output ) - the full scale analog output level is specified in the analog char- acteristics specification table. gnd 8 ground ( input ) - ground reference. va 9 analog power ( input ) - positive power for the analog and digital sections. aoutr 10 right channel analog output ( output ) - the full scale analog output level is specified in the analog characteristics specification table. sdin aoutr dem /sclk va lrck gnd mclk aoutl vq filt+ 1 2 3 4 5 6 7 8 9 10
ds613f1 5 cs4344/5/6/8 2. characteristics and specifications (all min/max characteristics and specif ications are guaranteed over the spec ified operating conditions. typical performance characteristics and specif ications are derived from measurements taken at nominal supply voltage and t a = 25 c.) specified operating conditions (agnd = 0 v; all voltages with respect to ground.) absolute maximum ratings (agnd = 0 v; all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameters symbol min nom max units dc power supply va 4.75 3.00 5.0 3.3 5.25 3.47 v v specified temperature range -czz -dzz t a -10 -40 - - +70 +85 c c parameters symb ol min max units dc power supply va -0.3 6.0 v input current, any pin except supplies i in -10ma digital input voltage v ind -0.3 va+0.4 v ambient operating temper ature (power applied) t op -55 125 c storage temperature t stg -65 150 c
6 ds613f1 cs4344/5/6/8 dac analog characteristics (full-scale output sine wave, 997 hz (note 1) , fs = 48/96/192 khz; test load r l = 3 k ? , c l = 10 pf ( figure 1 ). measurement bandwidth 10 hz to 20 khz, unless othe rwise specified.) notes: 1. one-half lsb of triangular pdf dither added to data. dac analog characteri stics - all modes parameter 5v nom 3.3v nom min typ max min typ max unit dynamic performance for cs43 44/5/6/8-czz (-10 to 70c) dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 99 96 90 87 105 102 96 93 - - - - 97 94 90 87 103 100 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -90 -82 -42 -90 -73 -33 -85 -76 -36 -84 -67 -27 - - - - - - -90 -80 -40 -90 -73 -33 -85 -74 -34 -84 -67 -27 db db db db db db dynamic performance for cs 4344/5-dzz (-40 to 85c) dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 95 92 86 83 105 102 96 93 - - - - 93 90 86 83 103 100 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -90 -82 -42 -90 -73 -33 -82 -72 -32 -82 -63 -23 - - - - - - -90 -80 -40 -90 -73 -33 -82 -70 -30 -82 -63 -23 db db db db db db parameter symbol min typ max unit interchannel isolation (1 khz) - 100 - db dc accuracy interchannel gain mismatch - 0.1 0.25 db gain drift - 100 - ppm/c analog output full scale output voltage 0.60?va 0.65?va 0.70?va vpp quiescent voltage v q -0.5?va-vdc max dc current draw from an aout pin i outmax -10- a max current draw from vq i qmax - 100 - a max ac-load resistance (see figure 2 on page 8 )r l -3-k ? max load capacitance (see figure 2 on page 8 )c l - 100 - pf output impedance z out - 100 - ?
ds613f1 7 cs4344/5/6/8 combined interpolation & on-c hip analog filter response (the filter characteristics have been normalized to the sample rate (fs) and can be referenced to the desired sam- ple rate by multiplying the give n characteristic by fs.) see (note 6) notes: 2. response is clock depend ent and will scale with fs. 3. for single-speed mode, the measurement bandwidth is 0.5465 fs to 3 fs. for double-speed mode, the measurement bandwidth is 0.577 fs to 1.4 fs. for quad-speed mode, the measurement bandwidth is 0.7 fs to 1 fs. 4. refer to figure 2 . 5. de-emphasis is available only in single-speed mode. 6. amplitude vs. frequency plots of this data are available in ?filter plots? on page 18 . parameter symbol min typ max unit combined digital and on-chip analog filter responsesingle-speed mode passband (note 2) to -0.1 db corner to -3 db corner 0 0 - - .35 .4992 fs fs frequency response 10 hz to 20 khz -.175 - +.01 db stopband .5465 - - fs stopband attenuation (note 3) 50 - - db group delay tgd - 10/fs - s de-emphasis error (note 5) fs = 32 khz fs = 44.1 khz fs = 48 khz - - - - - - +1.5/+0 +.05/-.25 -.2/-.4 db db db combined digital and on-chip analog filter responsedouble-speed mode passband (note 2) to +0.1 db corner to -3 db corner 0 0 - - .22 .501 fs fs frequency response 10 hz to 20 khz -.15 - +.15 db stopband .5770 - - fs stopband attenuation (note 3) 55 - - db group delay tgd - 5/fs - s combined digital and on-chip anal og filter responsequad-speed mode passband (note 2) to -0.1 db corner to -3 db corner 0 0 - - 0.110 0.469 fs fs frequency response 10 hz to 20 khz -.12 - +0 db stopband 0.7 - - fs stopband attenuation (note 3) 51 - - db group delay tgd - 2.5/fs - s
8 ds613f1 cs4344/5/6/8 digital input characteristics 7. i in for lrck is 20 a max. power and therma l characteristics 8. current consumption increases with increasing fs and increasing mclk. typ and max values are based on highest fs and highest mclk. variance between speed modes is small. 9. power down mode is defined when all clock and data lines are held static. 10. valid with the recommended capacitor values on vq and filt+ as shown in the typical connection di- agram in section 3 . figure 1. output test load figure 2. maximum loading parameters symbol min typ max units high-level input voltage (% of va) v ih 60% - - v low-level input voltage (% of va) v il - - 30% v input leakage current (note 7) i in --10 a input capacitance - 8 - pf 5 v nom 3.3 v nom parameters symbol min typ max min typ max units power supplies power supply current normal operation (note 8) power-down state (note 9) i a i a - - 22 220 30 - - - 16 100 21 - ma a power dissipation normal operation power-down state (note 9) - - 110 1.1 150 - - - 53 0.33 69 - mw mw package thermal resistance ja -95- -95-c/watt power supply rejection ratio (note 8) (1 khz) (60 hz) psrr - - 50 40 - - - - 50 40 - - db db aoutx agnd 3.3 f v out r l c l 100 50 75 25 2.5 51015 safe operating region capacitive load -- c (pf) l resistive load -- r (k ? ) l 125 3 20
ds613f1 9 cs4344/5/6/8 switching characteristics - serial audio interface 11. not all sample rates are supp orted for all clock ratios. see table 1, ?common clock frequencies,? on page 12 for supported ratio?s and frequencies. 12. in internal sclk mode, the duty cycle must be 50% +/? 1/2 mclk period. 13. the sclk / lrck ratio may be either 32, 48, 64 , or 72. this ratio depends on part type and mclk/lrck ratio. (see figures 7 - 9 ) parameters symbol min typ max units mclk frequency 0.512 - 50 mhz mclk duty cycle 45 - 55 % input sample rate all mc lk/lrck ratios combined (note 11) 256x, 384x, 1024x 256x, 384x 512x, 768x 1152x 128x, 192x 64x, 96x 128x, 192x fs 2 2 84 42 30 50 100 168 200 50 134 67 34 100 200 200 khz khz khz khz khz khz khz khz external sclk mode lrck duty cycle (external sclk only) 45 50 55 % sclk pulse width low t sclkl 20 - - ns sclk pulse width high t sclkh 20 - - ns sclk duty cycle 45 50 55 % sclk rising to lrck edge delay t slrd 20 - - ns sclk rising to lrck edge setup time t slrs 20 - - ns sdin valid to sclk rising setup time t sdlrs 20 - - ns sclk rising to sdin hold time t sdh 20 - - ns internal sclk mode lrck duty cycle (internal sclk only) (note 12) -50-% sclk period (note 13) t sclkw --ns sclk rising to lrck edge t sclkr -- s sdin valid to sclk rising setup time t sdlrs --ns sclk rising to sdin hold time mclk / lrck =1152, 1024, 512, 256, 128, or 64 t sdh --ns sclk rising to sdin hold time mclk / lrck = 768, 384, 192, or 96 t sdh --ns 10 9 sclk ---------------- tsclkw 2 ----------------- - 10 9 512 ( ) fs - -------------------- -10 + 10 9 512 ( ) fs - -------------------- -15 + 10 9 384 ( ) fs - -------------------- -15 +
10 ds613f1 cs4344/5/6/8 figure 3. external serial mode input timing figure 4. internal serial mode input timing figure 5. internal serial clock generation sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck sdata *internal sclk lrck sclkw t sdlrs t sdh t sclkr t the sclk pulses shown are internal to the cs4344/5/6/8. sdata lrck mclk *internal sclk 1 n 2 n * the sclk pulses shown are internal to the cs4344/5/6/8. n equals mclk divided by sclk
ds613f1 11 cs4344/5/6/8 3. typical conn ection diagram figure 6. recommended connection diagram dem/sclk 8 audio data processor external clock mclk agnd aoutr cs4344 cs4345 CS4346 cs4348 sdin lrck va aoutl 3 1 2 4 9 0.1 f + 1f 7 left audio output 10 right audio output +3.3 v to +5 v 3.3 f 10 k ? c 470 ? + r + 470 c= 4 fs(r 470) r ext 3.3 f 10 k ? c 470 ? + r ext ext ext + 0.1 f 10 f + *3.3 f 6 vq filt+ 5 note* note* = this circuitry is intended for applications where the cs4344/5/6/8 connects directly to an unbalanced output of the design. for internal routing applications please see the dac analog output characteristics for loading limitations. for best 20 khz response f *10 *popguard ramp can be adjusted by selecting this capacitor value to be 3.3 f to give 250 ms ramp time or 10 f to give a 420 ms ramp time. or
12 ds613f1 cs4344/5/6/8 4. applications the cs4344 family accepts data at standard audio sample rates including 48, 44.1 and 32 khz in ssm, 96, 88.2 and 64 khz in dsm, and 192, 176.4 and 128 khz in qsm. audio data is input via the serial data input pin (sdin). the left/right clock (lrck) determines which channel is currently being input on sdin, and the optional serial clock (sclk) clocks audio data into the input data buffer. the cs4344/5/6/8 di ffer in serial data formats as shown in figures 7 - 10 . 4.1 master clock mclk/lrck must be an integer ratio as shown in table 1 . the lrck frequency is equal to fs, the frequen- cy at which words for each channel are input to the device. the mclk-to-lrck frequency ratio and speed mode is detected automatically during the initialization sequence by counting the number of mclk transi- tions during a single lrck period and by detecting the absolute speed of mclk. internal dividers are set to generate the proper clocks. table 1 illustrates several standard audi o sample rates and the required mclk and lrck frequencies. please note there is no required phase relationship, but mclk, lrck and sclk must be synchronous. table 1. common clock frequencies 4.2 serial clock the serial clock controls the shifti ng of data into the input data buffers. the cs4344 family supports both external and internal serial clock generation modes. refer to figures 7 - 10 for data formats. 4.2.1 external serial clock mode the cs4344 family w ill enter the external serial clock mode wh en 16 low to high transitions are detected on the dem /sclk pin during any phase of the lrck period. when this mode is enabled, the internal se- rial clock mode and de-emphasis filt er cannot be accessed. the cs4344 fa mily will switch to internal se- rial clock mode if no low to high transitions are detected on the dem /sclk pin for 2 consecutive frames of lrck. refer to figure 12 . 4.2.2 internal serial clock mode in the internal serial clock mode, the serial clock is internally derived and synchronous with mclk and lrck. the sclk/lrck frequency ratio is either 32, 48, 64, or 72 depending upon data format. operation in this mode is identical to operat ion with an external serial clock synchronized with lrck. this mode al- lows access to the digital de-emphasis function. refer to figures 7 - 12 for details. lrck (khz) mclk (mhz) 64x 96x 128x 192x 256x 384x 512x 768x 1024x 1152x 32 - --- 8.1920 12.2880 - - 32.7680 36.8640 44.1 - --- 11.2896 16.9344 22.5792 33.8680 45.1580 - 48 - --- 12.2880 18.4320 24.5760 36.8640 49.1520 - 64 - - 8.1920 12.2880 - - 32.7680 49.1520 - - 88.2 - - 11.2896 16.9344 22.5792 33.8680 - - - - 96 - - 12.2880 18.4320 24.5760 36.8640 - - - - 128 8.1920 12.2880 - - 32.7680 49.1520 - - - - 176.4 11.2896 16.9344 22.5792 33.8680 - - - - - - 192 12.2880 18.4320 24.5760 36.8640 - - - - - - mode qsm dsm ssm
ds613f1 13 cs4344/5/6/8 figure 7. cs4344 data format (i 2 s) figure 8. cs4345 data format (left justified) lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode i2s, 16-bit data and int sclk = 32 fs if mclk/lrck = 1024, 512, 256, 128, or 64 i2s, up to 24-bit data and int sclk = 48 fs if mclk/lrck = 768, 384, 192, or 96 i2s, up to 24-bit data and int sclk = 72 fs if mclk/lrck = 1152 i2s, up to 24-bit data data valid on rising edge of sclk lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode left-justified, up to 24-bit data int sclk = 64 fs if mclk/lrck = 1024, 512, 256, 128, or 64 int sclk = 48 fs if mclk/lrck = 768, 384, 192, or 96 int sclk = 72 fs if mclk/lrck = 1152 left-justified, up to 24-bit data data valid on rising edge of sclk
14 ds613f1 cs4344/5/6/8 figure 9. CS4346 data format (right justified 24) figure 10. cs4348 data format (right justified 16) lrck sclk left channel sdata 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel internal sclk mode external sclk mode right justified, 24-bit data int sclk = 64 fs if mclk/lrck = 1024, 512, 256, 128, or 64 int sclk = 48 fs if mclk/lrck = 768, 384, 192, or 96 int sclk = 72 fs if mclk/lrck = 1152 right justified, 24-bit data data valid on rising edge of sclk sclk must have at least 48 cycles per lrck period lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks internal sclk mode external sclk mode right justified, 16-bit data int sclk = 32 fs if mclk/lrck = 1024, 512, 256, 128, or 64 int sclk = 48 fs if mclk/lrck = 768, 384, 192, or 96 int sclk = 72 fs if mclk/lrck = 1152 right justified, 16-bit data data valid on rising edge of sclk sclk must have at least 32 cycles per lrck period
ds613f1 15 cs4344/5/6/8 4.3 de-emphasis the cs4344 family includes on-chip digital de-emphasis. figure 11 shows the de-emphasis curve for fs equal to 44.1 khz. the frequency re sponse of the de-emphasis curve w ill scale proportionally with changes in sample rate, fs. the de-emphasis filter is active (inactive) if the dem /sclk pin is low (high) for 5 consecutive falling edges of lrck. this function is available only in the internal serial clock mode . figure 11. de-emphasis curve (fs = 44.1khz) 4.4 initialization and power-down the initialization and power-down sequence flow chart is shown in figure 12 . the cs4344 family enters the power-down state upon initial power-up. the interpolation filters and delta-sigma modulators are reset, and the internal voltage reference, multi-bit digital-to-analog converters and switched-capacitor low-pass filters are pow- ered down. the device will remain in the power-down mode un til mclk and lrck are present. once mclk and lrck are detected, mclk occurrences are counted ov er one lrck period to determine the mclk/lrck fre- quency ratio. power is then applied to the internal volt age reference. finally, power is applied to the d/a converters and switched-capacitor filters, and the analog outputs will ramp to the quiescent voltage, vq. 4.5 output transient control the cs4344 family uses popguard ? technology to minimize the effect s of output transients during power- up and power-down. this technique eliminates the audio transients commonly produced by single-ended single-supply converters when it is implemented with external dc-blocking capacitors connected in series with the audio outputs. to make best use of this fe ature, it is necessary to understand its operation. 4.5.1 power-up when the device is initially powered-up, the audio outputs, aoutl and aoutr, are clamped to vq which is initially low. after mc lk is applied the outputs begin to ramp with vq towards the nominal quiescent voltage. this ramp takes approximately 250 ms with a 3.3 f cap connected to vq (420 ms with a 10 f connected to vq) to complete. the gradual voltage ramping allows time for the external dc-blocking ca- pacitors to charge to vq, effectively blocking the quiescent dc voltage. once valid lrck and sdin are supplied (and sclk if used) approximately 2000 sample periods later audio output begins. 4.5.2 power-down to prevent audio transients at power-down the dc-blocking capacitors must fully discharge before turning off the power. in order to do this mclk should be stopped for a period of about 250 ms for a 3.3 f cap connected to vq (420 ms for a 10 f cap connected to vq) before removing power. during this time volt- age on vq and the audio outputs discharge gradually to gnd. if power is removed before this time period has passed a transient will occur when the va supply drops below that of vq. there is no minimum time for a power cycle, power may be re-applied at any time. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz
16 ds613f1 cs4344/5/6/8 when changing clock ratio or sample rate it is recommend ed that zero data (or near zero data) be present on sdin for at least 10 lrck samples before the change is made . during the clocking change the dac outputs will always be in a zero data state. if no zero aud io is present at the time of switching, a slight click or pop may be heard as the dac output automatically goes to it?s zero data state. figure 12. cs4344/5/6/8 initiali zation and power-down sequence user: apply power wait state user: apply lrck mclk/lrck ratio detection user: applied sclk user: remove lrck user: change mclk/lrck ratio sclk mode = internal sclk mode = external normal operation de-emphasis available analog output is generated normal operation de-emphasis not available analog output is generated user: change mclk/lrck ratio user: remove mclk user: remove lrck user: remove mclk user: apply mclk power-down state vq and outputs low vq and outputs ramp down vq and outputs ramp down vq and outputs ramp up user: no sclk
ds613f1 17 cs4344/5/6/8 4.6 grounding and power supply decoupling as with any high resolution converter, the cs4344 fa mily requires careful attention to power supply and grounding arrangements to optimize performance. figure 6 shows the recommended power arrangement with va connected to a clean +3.3 v or +5 v supply. for best performance, decoupling and filter capacitors should be located as close to the device package as possible with the sma llest capacitors closest. 4.7 analog output and filtering the analog filter present in the cs4344 family is a sw itched-capacitor filter followed by a continuous time low pass filter. its response, combined with t hat of the digital interpolator, is given in figures 13 - 20 . the recommended external analog circuitry is shown in the ?typical connection diagram? on page 11 .
18 ds613f1 cs4344/5/6/8 5. filter plots figure 13. single-speed stopband rejectio n figure 14. single-speed transition band 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -0.25 -0. 2 -0.15 -0. 1 -0.05 0 0.05 frequency (normalized to fs) amplitude db figure 15. single-speed transition band figure 16. single-speed passband ripple 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 frequency (normalized to fs) amplitude db
ds613f1 19 cs4344/5/6/8 figure 17. double-speed stopband rejection figure 18. double-speed transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 1 frequency (normalized to fs) amplitude db 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -0. 2 -0. 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 frequency (normalized to fs) amplitude db figure 19. double-speed transition band figure 20. double-speed passband ripple
20 ds613f1 cs4344/5/6/8 figure 21. quad-speed stopband rejectio n figure 22. quad-speed transition band 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 -60 -50 -40 -30 -20 -10 0 amplitude (db) frequency(normalized to fs) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 amplitude (db) frequency(normalized to fs) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -1. 5 -1 -0. 5 0 frequency (normalized to fs) amplitude db figure 23. quad-speed transition band figure 24. quad-speed passband ripple 0.4 0.45 0.5 0.55 0.6 0.65 0.7 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 amplitude (db) frequency(normalized to fs)
ds613f1 21 cs4344/5/6/8 6. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-n oise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measure- ment to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement te chnique has been accepted by the audio engineer- ing society, aes17-1991, and the electronic indu stries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right ch annels. measured for each channel at the converter's output with all zeros to the input under test and a fu ll-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c.
22 ds613f1 cs4344/5/6/8 7. package dimensions notes: 1. reference document: jedec mo-187 2. d does not include mold flash or protru sions which is 0.15 mm max. per side. 3. e1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. dimension b does not include a total allowable dambar protrusion of 0.08 mm max. 5. exceptions to jedec dimension. inches millimeters note dim min nom max min nom max a -- -- 0.0433 -- -- 1.10 a1 0 -- 0.0059 0 -- 0.15 a2 0.0295 -- 0.0374 0.75 -- 0.95 b 0.0059 -- 0.0118 0.15 -- 0.30 4 , 5 c 0.0031 -- 0.0091 0.08 -- 0.23 d -- 0.1181 bsc -- -- 3.00 bsc -- 2 e -- 0.1929 bsc -- -- 4.90 bsc -- e1 -- 0.1181 bsc -- -- 3.00 bsc -- 3 e -- 0.0197 bsc -- -- 0.50 bsc -- l 0.0157 0.0236 0.0315 0.40 0.60 0.80 l1 -- 0.0374 ref -- -- 0.95 ref -- 0 -- 8 0 -- 8 controlling dimensi on is millimeters 10ld tssop (3 mm body) package drawing e n 1 23 e b a1 a2 a d seating plane e1 1 l side view end view top view l1 c
ds613f1 23 cs4344/5/6/8 8. ordering information 8.1 functional compatibility cs4334-ks ? cs4344-czz cs4335-ks ? cs4345-czz cs4336-ks ? CS4346-czz cs4338-ks ? cs4348-czz cs4334-bs ? cs4344-dzz cs4334-ds ? cs4344-dzz 8.2 selection guide the cs4344 family differs by serial audio format as follows: ? cs4344 ? 16 to 24-bit, i2s ? cs4345 ? 16 to 24-bit, left-justified ? CS4346 ? 24-bit, right-justified ? cs4348 ? 16-bit, right-justified product description package pb-free grade temp range container order # cs4344 24-bit, 192 khz stereo d/a converter 10-tssop yes commercial -10 to +70 c tube or tape and reel cs4344-czz automotive -40 to +85 c cs4344-dzz cs4345 commercial -10 to +70 c cs4345-czz automotive -40 to +85 c cs4345-dzz CS4346 commercial -10 to +70 c CS4346-czz cs4348 cs4348-czz
24 ds613f1 cs4344/5/6/8 9. revision history release date changes pp3 august 2005 corrected thd+n typ and max performance f1 september 2005 -updated passband and frequency response specifications in ?combined interpolation & on-chip analog filter response? on page 7 -updated psrr specification -updated vih specification -updated figures in ?filter plots? on page 18 contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com/corporate/contacts/sales.cfm important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warran ty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential ri sks of death, personal injury, or severe prop- erty or environmental damage (? critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military a pplications, products s urgically implanted into the body, automotive sa fety or security de- vices, life support products or other cri tical applications. inclus ion of cirrus products in s uch applications is under- stood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, the cirrus logic logo designs , and popguard are trademarks of cirrus logic, inc. all other brand and pr oduct names in this document may be trademarks or service marks of their respective owners.

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